-------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity endian_2 is
end endian_2;
architecture Behavioral of endian_2 is
constant C_OPB_AWIDTH : integer := 32; signal temp1 : std_logic_vector(31 downto 0) := x"9999_9999"; --1001,1001,... signal temp2 : std_logic_vector(0 to 31) := x"5555_5555"; --...,0101,0101 signal result1 : std_logic_vector(2 downto 0); signal result2 : std_logic_vector(2 downto 0);
subtype ADDR_CHK1 is natural range C_OPB_AWIDTH-3 downto C_OPB_AWIDTH-5; --29,28,27 bit subtype ADDR_CHK2 is natural range C_OPB_AWIDTH-5 to C_OPB_AWIDTH-3; --27,28,29 bit
begin
result1 <= temp1(ADDR_CHK1);--should be 01,1 result2 <= temp2(ADDR_CHK2);--should be 1,01
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity endian_2 is
end endian_2;
architecture Behavioral of endian_2 is
constant C_OPB_AWIDTH : integer := 32;
signal temp1 : std_logic_vector(31 downto 0) := x"9999_9999"; --1001,1001,...
signal temp2 : std_logic_vector(0 to 31) := x"5555_5555"; --...,0101,0101
signal result1 : std_logic_vector(2 downto 0);
signal result2 : std_logic_vector(2 downto 0);
subtype ADDR_CHK1 is natural range C_OPB_AWIDTH-3 downto C_OPB_AWIDTH-5; --29,28,27 bit
subtype ADDR_CHK2 is natural range C_OPB_AWIDTH-5 to C_OPB_AWIDTH-3; --27,28,29
bit
begin
result1 <= temp1(ADDR_CHK1);--should be 01,1
result2 <= temp2(ADDR_CHK2);--should be 1,01
end Behavioral;
subtype natural is integer range 0 to integer'high; --(2^31 - 1)
subtype positive is integer range 1 to integer'high; --(2^31 - 1)