Feb
7
Xilinx Answer Record 18181
Virtex-II/-II Pro/-4 - What are the rules for cascading two DCMs in series?
The recommendations for cascading DCMs are as follows:
- Do not cascade DCMs unless it is absolutely necessary; jitter accumulates when the DCMs are cascaded. Consequently, the output clock jitter of the second stage DCM is worse than the output clock jitter of the first stage DCM. If possible, implement your application using two DCMs in parallel instead of in series.
- Due to the accumulative nature of the DCM jitter, Xilinx does not recommend cascading CLKFX to CLKFX in high-frequency mode (see details below on how to calculate accumulative jitter).
- If the frequency of the DCM inputs allow it, use feedback for both DCMs.
- Use the inverted LOCKED of DCM1 to create reset of DCM2. For Virtex-II and Virtex-II Pro, the recommended length of a reset pulse is three CLKIN cycles. Consequently, Xilinx recommends using the inverted LOCKED of DCM1 as the input to an SRL16 and the output of the SRL16 as the reset input of DCM2. See the Virtex-4 Data Sheet for information on the minimum reset pulse required for the DCM.
- Use a dedicated clock line for CLKFX/CLK2X to CLKIN connection (i.e., through a BUFG).
- You are required to meet the input and output frequency and jitter specifications for each DCM.
- M/D ratio:
M and D values range per data sheet
R1 = M/D ratio for DCM1
R2 = M/D ratio for DCM2
Recommended: R1 > R2 (if possible)
- Jitter: the output jitter specifications for DLL outputs are provided in the data sheet. Use the Architecture Wizard to determine the jitter for CLKFX. Remember that Fin2 = Fin1 * M1 / D1, and then calculate the quadratic value. Jitter = Square Root (Jitter1*Jitter1 + Jitter2*Jitter2).
Cascading Example
Virtex-II/-II Pro/-4 - What are the rules for cascading two DCMs in series?
The recommendations for cascading DCMs are as follows:
- Do not cascade DCMs unless it is absolutely necessary; jitter accumulates when the DCMs are cascaded. Consequently, the output clock jitter of the second stage DCM is worse than the output clock jitter of the first stage DCM. If possible, implement your application using two DCMs in parallel instead of in series.
- Due to the accumulative nature of the DCM jitter, Xilinx does not recommend cascading CLKFX to CLKFX in high-frequency mode (see details below on how to calculate accumulative jitter).
- If the frequency of the DCM inputs allow it, use feedback for both DCMs.
- Use the inverted LOCKED of DCM1 to create reset of DCM2. For Virtex-II and Virtex-II Pro, the recommended length of a reset pulse is three CLKIN cycles. Consequently, Xilinx recommends using the inverted LOCKED of DCM1 as the input to an SRL16 and the output of the SRL16 as the reset input of DCM2. See the Virtex-4 Data Sheet for information on the minimum reset pulse required for the DCM.
- Use a dedicated clock line for CLKFX/CLK2X to CLKIN connection (i.e., through a BUFG).
- You are required to meet the input and output frequency and jitter specifications for each DCM.
- M/D ratio:
M and D values range per data sheet
R1 = M/D ratio for DCM1
R2 = M/D ratio for DCM2
Recommended: R1 > R2 (if possible)
- Jitter: the output jitter specifications for DLL outputs are provided in the data sheet. Use the Architecture Wizard to determine the jitter for CLKFX. Remember that Fin2 = Fin1 * M1 / D1, and then calculate the quadratic value. Jitter = Square Root (Jitter1*Jitter1 + Jitter2*Jitter2).
Cascading Example
