Feb
16
从Xapp700中摘录的一段：（针对V4）
1、IDELAYCTRL模块是为了给tap delay line一个绝对的参考电压
2、每一个CLOCK REGION一个IDELAYCTRL
3、IDELAYCTRL的REFCLK需要一个200MHz时钟，占用全局时钟走线
4、IDELAYCTRL如果不加LOC约束，MAP就会启用并复制属性给所有的IDELAYCTRL，并在最后的RDY信号后加与门，这样会在每个CLOCK REGION都占用掉一个全局时钟走线（当然也有RST和RDY的走线）
关于IDELAYCTRL的更多信息，察看UG070
1、IDELAYCTRL模块是为了给tap delay line一个绝对的参考电压
2、每一个CLOCK REGION一个IDELAYCTRL
3、IDELAYCTRL的REFCLK需要一个200MHz时钟，占用全局时钟走线
4、IDELAYCTRL如果不加LOC约束，MAP就会启用并复制属性给所有的IDELAYCTRL，并在最后的RDY信号后加与门，这样会在每个CLOCK REGION都占用掉一个全局时钟走线（当然也有RST和RDY的走线）
关于IDELAYCTRL的更多信息，察看UG070
Feb
14
参考资料：
UG070: Virtex 4 User Guide Chapter 6-8
Xapp705: Virtex-4 High-Speed Dual Data Rate LVDS Transceiver
Xapp707: Advanced ChipSync Applications application note
Xapp700: Dynamic Phase Alignment for Networking Applications
Xilinx Customer Training Course:
Design for Performance
Design with Virtex 4
UG070: Virtex 4 User Guide Chapter 6-8
Xapp705: Virtex-4 High-Speed Dual Data Rate LVDS Transceiver
Xapp707: Advanced ChipSync Applications application note
Xapp700: Dynamic Phase Alignment for Networking Applications
Xilinx Customer Training Course:
Design for Performance
Design with Virtex 4
Feb
7
Xilinx Answer Record 18181
Virtex-II/-II Pro/-4 - What are the rules for cascading two DCMs in series?
The recommendations for cascading DCMs are as follows:
- Do not cascade DCMs unless it is absolutely necessary; jitter accumulates when the DCMs are cascaded. Consequently, the output clock jitter of the second stage DCM is worse than the output clock jitter of the first stage DCM. If possible, implement your application using two DCMs in parallel instead of in series.
- Due to the accumulative nature of the DCM jitter, Xilinx does not recommend cascading CLKFX to CLKFX in high-frequency mode (see details below on how to calculate accumulative jitter).
- If the frequency of the DCM inputs allow it, use feedback for both DCMs.
- Use the inverted LOCKED of DCM1 to create reset of DCM2. For Virtex-II and Virtex-II Pro, the recommended length of a reset pulse is three CLKIN cycles. Consequently, Xilinx recommends using the inverted LOCKED of DCM1 as the input to an SRL16 and the output of the SRL16 as the reset input of DCM2. See the Virtex-4 Data Sheet for information on the minimum reset pulse required for the DCM.
- Use a dedicated clock line for CLKFX/CLK2X to CLKIN connection (i.e., through a BUFG).
- You are required to meet the input and output frequency and jitter specifications for each DCM.
- M/D ratio:
M and D values range per data sheet
R1 = M/D ratio for DCM1
R2 = M/D ratio for DCM2
Recommended: R1 > R2 (if possible)
- Jitter: the output jitter specifications for DLL outputs are provided in the data sheet. Use the Architecture Wizard to determine the jitter for CLKFX. Remember that Fin2 = Fin1 * M1 / D1, and then calculate the quadratic value. Jitter = Square Root (Jitter1*Jitter1 + Jitter2*Jitter2).
Cascading Example
Virtex-II/-II Pro/-4 - What are the rules for cascading two DCMs in series?
The recommendations for cascading DCMs are as follows:
- Do not cascade DCMs unless it is absolutely necessary; jitter accumulates when the DCMs are cascaded. Consequently, the output clock jitter of the second stage DCM is worse than the output clock jitter of the first stage DCM. If possible, implement your application using two DCMs in parallel instead of in series.
- Due to the accumulative nature of the DCM jitter, Xilinx does not recommend cascading CLKFX to CLKFX in high-frequency mode (see details below on how to calculate accumulative jitter).
- If the frequency of the DCM inputs allow it, use feedback for both DCMs.
- Use the inverted LOCKED of DCM1 to create reset of DCM2. For Virtex-II and Virtex-II Pro, the recommended length of a reset pulse is three CLKIN cycles. Consequently, Xilinx recommends using the inverted LOCKED of DCM1 as the input to an SRL16 and the output of the SRL16 as the reset input of DCM2. See the Virtex-4 Data Sheet for information on the minimum reset pulse required for the DCM.
- Use a dedicated clock line for CLKFX/CLK2X to CLKIN connection (i.e., through a BUFG).
- You are required to meet the input and output frequency and jitter specifications for each DCM.
- M/D ratio:
M and D values range per data sheet
R1 = M/D ratio for DCM1
R2 = M/D ratio for DCM2
Recommended: R1 > R2 (if possible)
- Jitter: the output jitter specifications for DLL outputs are provided in the data sheet. Use the Architecture Wizard to determine the jitter for CLKFX. Remember that Fin2 = Fin1 * M1 / D1, and then calculate the quadratic value. Jitter = Square Root (Jitter1*Jitter1 + Jitter2*Jitter2).
Cascading Example
Feb
5
Clock Jetter分为两种：Cycle-to-cycle Jitter和Period jitter。
Cycle-to-cycle Jitter：即每个clock cycle的差异。第一个输出是1000 ns，第二个是1001 ns，那么+1ns就是cycle2cycle了。Spartan3的DCM cycle-to-cycle是150~300ps
Period jitter 是Cycle-to-cycle 的一种总体的统计表现。
参考资料：
xapp462 [PDF]
Cycle-to-cycle Jitter：即每个clock cycle的差异。第一个输出是1000 ns，第二个是1001 ns，那么+1ns就是cycle2cycle了。Spartan3的DCM cycle-to-cycle是150~300ps
Period jitter 是Cycle-to-cycle 的一种总体的统计表现。
参考资料：
xapp462 [PDF]
Feb
4
1、检查布局布线结果——检查DCM，BRAM，Slice，IOB等等的配置方式；查看布线方式，是不是走了全局布线通道等。
2、修改DCM, BRAM, Slice, IOB等的配置方式，比如修改DCM倍频系数，Pin的输出电压标准等
3、与Timing Analyzer配合实现CrossProbing，查看Timing瓶颈
4、添加Probe，将内部信号引到Pin上以方便示波器观察（可直接生成bit文件）
5、更改ChipScope的ILA Core的一些配置，比如说改变ILA采样时钟。
6、更改布局，比如说，换一个Pin来输出信号
7、改变布线
8、Direct Routing，将所有的布局布线信息都记录下来
2、修改DCM, BRAM, Slice, IOB等的配置方式，比如修改DCM倍频系数，Pin的输出电压标准等
3、与Timing Analyzer配合实现CrossProbing，查看Timing瓶颈
4、添加Probe，将内部信号引到Pin上以方便示波器观察（可直接生成bit文件）
5、更改ChipScope的ILA Core的一些配置，比如说改变ILA采样时钟。
6、更改布局，比如说，换一个Pin来输出信号
7、改变布线
8、Direct Routing，将所有的布局布线信息都记录下来
